亚洲精品55夜色66夜色_无码视频一区二区三区线观看_亚洲欧美日韩在线码_色欲悠久久久久综合网日本

說明

The VCE6467T, AVCE6467T leverages TI's DaVinci™ technology to meet the networked media encode and decode digital media processing needs of next-generation embedded devices.

Throughout this document, unless otherwise noted, VCE6467T, refer to the VCE6467T and AVCE6467T devices.

The VCE6467T enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, high processing performance, and long battery life through the maximum flexibility of a fully integrated mixed processor solution.

The dual-core architecture of the VCE6467T provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C64x+ DSP core and an ARM926EJ-S core.

特性

• High-Performance Digital Media SoC
  • 1-GHz C64x+™ Clock Rate
  • 500-MHz ARM926EJ-S™ Clock Rate
  • Eight 32-Bit C64x+ Instructions/Cycle
  • 8000 C64x+ MIPS
  • Fully Software-Compatible With C64x / ARM9™
  • Industrial Temperature Devices Available
• Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
  • Eight Highly Independent Functional Units
    • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
    • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
  • Load-Store Architecture With Non-Aligned Support
  • 64 32-Bit General-Purpose Registers
  • Instruction Packing Reduces Code Size
  • All Instructions Conditional
  • Additional C64x+™ Enhancements
    • Protected Mode Operation
    • Exceptions Support for Error Detection and Program Redirection
    • Hardware Support for Modulo Loop Operation
• C64x+ Instruction Set Features