SPC56EL54L5
Features
■ High-performance e200z4d dual core
– 32-bit Power Architecture® technology CPU
– Core frequency as high as 120 MHz
– Dual issue five-stage pipeline core
– Variable Length Encoding (VLE)
– Memory Management Unit (MMU)
– 4 KB instruction cache with error detection
code
– Signal processing engine (SPE)
■ Memory available
– Up to 1 MB flash memory with ECC
– Up to 128 KB on-chip SRAM with ECC
– Built-in RWW capabilities for EEPROM
emulation
■ SIL3/ASILD innovative safety concept:
LockStep mode and Fail-safe protection
– Sphere of replication (SoR) for key
components (such as CPU core, eDMA,
crossbar switch)
– Fault collection and control unit (FCCU)
– Redundancy control and checker unit
(RCCU) on outputs of the SoR connected
to FCCU
– Boot-time Built-In Self-Test for Memory
(MBIST) and Logic (LBIST) triggered by
hardware
– Boot-time Built-In Self-Test for ADC and
flash memory triggered by software
– Replicated safety enhanced watchdog
– Replicated junction temperature sensor
– Non-maskable interrupt (NMI)
– 16-region memory protection unit (MPU)
– Clock monitoring units (CMU)
– Power management unit (PMU)
– Cyclic redundancy check (CRC) unit
