IS61VF25618A
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Burst sequence control using MODE input
• Three chip enable option for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• Auto Power-down during deselect
• Single cycle deselect
• Snooze MODE for reduced-power standby
• Power Supply
LF: Vdd 3.3V + 5%, Vddq 3.3V/2.5V + 5%
VF: Vdd 2.5V -5% +10%, Vddq 2.5V -5% +10%
• JEDEC 100-Pin TQFP, 119-pin PBGA, and 165-
pin PBGA packages
• Automotive temperature available
• Lead-free available
DESCRIPTION
The ISSI IS61(64)LF12832A, IS64VF12832A, IS61(64)
LF/VF12836A and IS61(64)LF/VF25618A are high-speed,
low-power synchronous static RAMs designed to provide
burstable, high-performance memory for communication
and networking applications. The IS61(64)LF12832A is
organized as 131,072 words by 32 bits. The IS61(64)LF/
VF12836A is organized as 131,072 words by 36 bits. The
IS61(64)LF/VF25618A is organized as 262,144 words by
18 bits. Fabricated with ISSI's advanced CMOS technology,
the device integrates a 2-bit burst counter, high-speed
SRAM core, and high-drive capability outputs into a single
monolithic circuit. All synchronous inputs pass through
registers controlled by a positive-edge-triggered single
clock input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be one
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
Byte write operation is performed by using byte write enable
(BWE) input combined with one or more individual
byte write signals (BWx). In addition, Global Write (GW)
is available for writing all bytes at one time, regardless of
the byte write controls.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the ADV (burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW. Interleave
burst is achieved when this pin is tied HIGH or left floating.
