CY7C0241E-25AXCT
Features
■ True dual-ported memory cells that allow simultaneous reads
of the same memory location
■ 4K ×16 organization (CY7C024E)
■ 4K × 18 organization (CY7C0241E)
■ 8K × 16 organization (CY7C025E)
■ 8K × 18 organization (CY7C0251E)
■ 0.35-μ complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■ High-speed access: 15 ns
■ Low operating power: ICC = 180 mA (typ), ISB3 = 0.05 mA (typ)
■ Fully asynchronous operation
■ Automatic power-down
■ Expandable data bus to 32/36 bits or more using master/slave
chip select when using more than one device
■ On-chip arbitration logic
■ Semaphores included to permit software handshaking
between ports
■ INT flag for port-to-port communication
■ Separate upper-byte and lower-byte control
■ Pin select for master or slave
■ Available in Pb-free 100-pin thin quad flatpack (TQFP) package
