CY7C009V-25AXC
Features
■ True dual-ported memory cells which allow simultaneous
access of the same memory location
■ 128 K × 8 organization (CY7C009)
■ 0.35-micron CMOS for optimum speed/power
■ High-speed access: 15/20/25 ns
■ Low operating power
❐ Active: ICC = 115 mA (typical)
❐ Standby: ISB3 = 10 A (typical)
■ Fully asynchronous operation
■ Automatic power-down
■ Expandable data bus to 16 bits or more using Master/Slave
chip select when using more than one device
■ On-chip arbitration logic
■ Semaphores included to permit software handshaking
between ports
■ INT flag for port-to-port communication
■ Dual chip enables
■ Pin select for Master or Slave
■ Commercial and industrial temperature ranges
■ Available in 100-pin TQFP
■ Pb-free packages available
